Typical complementary metal-oxide-semiconductor (CMOS) image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. Once the integration cycle is complete, collected charge is converted into a voltage signal, which is supplied to output terminals of an image sensor. This charge to voltage conversion is performed within each sensor pixel. The pixel output voltage (i.e., an analog voltage signal) is transferred to the output terminals using various pixel addressing and scanning schemes. The analog voltage signal can also be converted on-chip to a digital equivalent before reaching the chip output.
The sensor pixels include buffer amplifiers (i.e., source followers) that drive sensing lines connected to the pixels through address transistors. After the charge to voltage conversion and after the resulting voltage signal has been read out from the pixels, the pixels are reset in preparation for a successive charge accumulation cycle. In pixels that include floating diffusions (FD) serving as charge detection nodes, the reset operation is performed by turning on a reset transistor that connects the floating diffusion node to a voltage reference.
Removing charge from the floating diffusion node using the reset transistor, however, generates kTC-reset noise as is well known in the art. The kTC noise must be removed using correlated double sampling (CDS) signal processing techniques in order to achieve desired low noise performance. Typical CMOS image sensors that utilize CDS require at least three or four transistors (4T) per pixel. An example of the 4T pixel circuit with a pinned photodiode can be found in Lee (U.S. Pat. No. 5,625,210).
In modern CMOS image sensor designs, circuitry associated with multiple photo-diodes may be shared, as can be found for example in Guidash U.S. Pat. No. 6,657,665. In Guidash, a sensor pixel consists of two photo-diodes located in neighboring rows. The two photo-diodes located in the neighboring rows share the same circuitry. Sharing circuitry in this way can result in having only two metal bus lines in the row direction and two metal bus lines in the column direction per photo-diode, as shown in FIG. 1.
This is useful for designing small pixels or pixels with high fill factor (FF), because the minimum pixel size is dependent on the spacing and width of the metal bus lines. This is also illustrated in FIG. 1, where drawing 100 represents the schematic diagram of a shared circuit pixel with two photo-diodes 107 and 108. Photo-diodes 107 and 108 are coupled to common floating diffusion charge detection node 115 through charge transfer transistors 109 and 110. FD node 115 is connected to the gate of source follower (SF) transistor 112. SF transistor 112 has a drain that is connected to Vdd column bus line 101 (i.e., a positive power supply line on which positive power supply voltage Vdd is provided) via line 116. SF transistor 112 has a source that is connected to output signal column bus line 102 via address (Sx) transistor 113 and line 117.
FD node 115 is reset using transistor 111. Reset transistor 111 has a drain that is connected to line 116 and a source that is connected to node 115. Address transistor 113, reset transistor 111, and charge transfer transistors 109 and 110 are controlled using control signals supplied over row bus lines 114, 106, 104, and 105, respectively.
As shown in FIG. 1, the circuit that has two photodiodes. This particular image sensor therefore has two row bus lines and two column bus lines per photodiode. In many cases, however, it is also necessary to provide an additional connection between transistor 110 and FD node 115, as indicated by wire 103. This additional connection reduces the pixel fill factor.
Photodiodes 107 and 108 are formed in a semiconductor substrate having a front surface and a back surface. The associated pixel transistors (i.e., reset transistor 111, charge transfer transistors 109 and 110, source follower transistor 112, and address transistor 113) are formed at the front surface of the substrate. A dielectric stack that includes metal interconnect layers and oxide layers may be formed over the pixel transistors on the front surface of the substrate.
In conventional front-side-illuminated image sensors, light enters the image sensor from the front side of the substrate. The quantum efficiency of photon-to-electron conversion may be reduced because the incoming light has to travel through the dielectric stack. Wires formed in the metal routing layers may obstruct a portion of the incoming light. The pixel well capacity (i.e., a pixel's capability to store electrons) may also be reduced when a large number of transistors are used, because the transistors take up valuable integrated circuit area that could instead be used to form a larger pixel charge storage well.
It may therefore be desirable to illuminate sensor pixels from the back surface of the substrate where no wiring is obstructing the light. It may also be desirable to adopt the bulk-charge-modulated-device (BCMD) configuration in which a single transistor is used for pixel addressing, charge sensing, signal buffering, and charge reset. Description of the BCMD concept can be found in U.S. Pat. No. 5,424,223 and U.S. Pat. No. 4,901,129 both to Hynecek, which are hereby incorporated by reference herein in their entireties.
In a conventional BCMD pixel, charge is stored under the channel of a BCMD transistor. The amount of stored charge modulates the BCMD transistor's threshold voltage. The change in threshold voltage is sensed when a current is directed to flow through the BCMD transistor. After charge sensing has been completed, the pixel is reset by removing the collected charged. In the conventional BCMD pixel, charge is removed from the pixel in a vertical direction. This may be a disadvantage if used in conjunction with the back-side-illumination (BSI) sensor arrangement, because the vertical structure of the reset transistor may block incoming light and reduce light sensitivity.
Lateral reset structures that provide charge reset in a horizontal direction (i.e., charge transfer parallel to the surface of the substrate) have previously been developed in BSI applications. For example, a lateral reset structure is described in U.S. Pat. No. 5,424,233 to Hynecek. Although this type of lateral reset structure is often satisfactory, in some applications, such as applications involving high resolution image sensors, further reductions in pixel size may be desired.
It would therefore be desirable to be able to provide improved image sensors.